CMOS technology is used not only for digital integrated circuits due to a low power dissipation, a high density of integration and a low cost of fabrication but also for analog integrated circuits. The most important applications that are using microelectronic components, such as telecommunication equipment, industrial control equipment, auto electronics, require more and more specialized integrated circuits. The continuing development in the semiconductors has led to implementation and use of gate arrays and standard cells as the most modern and inexpensive way to produce ASIC's, Application Specific Integrated Circuits. Gate arrays technologies have a special place in the ASIC design. An ASIC is an integrated circuit that can place on a single chip an entire system or a great part of it, performing not only digital, but also analog functions. A CMOS gate array can be simply described as a matrix of pre-manufactured identical cells that only requires the addition of the final metal and contact masks to define a new circuit function. The gate array technology can quickly respond to the customer requirements in a low cost and efficient manner. Gate arrays can be implemented in a variety of circuit and process technologies including most commonly static CMOS and bipolar emitter coupled logic.
One of the problems in static CMOS logic is the series connections of devices required in logic gates. FIGS. 1A and 1B illustrate the standard CMOS static gates. In static CMOS logic circuits each input, shown as A and B respectively, must drive two gates—the gate of one NMOS transistor and the gate of a PMOS transistor. This results in a large area for static CMOS circuits and a large number of metal wiring levels must be utilized to allow interconnections. FIG. 1A illustrates a 2-input positive logic NOR gate. In FIG. 1A, input A drives gates 102 and 104, and input B drives gates 106 and 108. FIG. 1B illustrates a 2-input positive logic NAND gate. In FIG. 1B, input A drives gates 112 and 114, and input B drives gates 116 and 118.
Another problem with static CMOS logic circuits is that in the PMOS transistor the hole mobility is about three times lower than the mobility of electrons if the transistors have comparable sizes. Because of this, switching transients are very asymmetrical. The charge up transient of the capacitive load in a simple inverter takes far longer than the discharge transient. To attempt to compensate, the PMOS transistors are often fabricated with a large width or size to provide symmetrical switching. However, this increases the stray capacitive loads and results in an even larger area for the circuits, and very inefficient area utilization.
A number of other approaches to overcome these shortcomings have been developed and are discussed further in the detailed description portion of the present application. However, as detailed therein, each presents or introduces new shortcomings to the circuit design.
For CMOS NOR gates or inverters being clocked at high frequencies where the dynamic switching power is comparable to the DC power of NMOS circuits another type of circuit configuration now commonly referred to as pseudo-nMOS is often employed. (See generally, H. Sakamoto and L. Forbes, “Grounded load complementary FET circuits; SCEPTRE analysis,” IEEE J. Solid-State Circuits, Vol. SC-8, No. 4, pp. 282–284, 1973; and J. M. Rabaey, “Digital integrated circuits, a design perspective,” Prentice Hall, Upper Saddle River, N.J., 1996, pp. 205–209). A pseudo-nMOS circuit configuration is shown in FIG. 2A. The pseudo-nMOS circuit configuration of FIG. 2A is often employed in CMOS inverters and NOR gates. (See generally, M. A. Krause et al., “Programmable logic array structures for CMOS VLSI 1983 International Electrical, Electronics Conference Proceedings, 26–28 Sep. 1983, Toronto, Ont., Canada, 26–28 Sep. 1983, vol. 2, pp. 304–7; and N. Subba et al., “pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design,” IEEE Int. SOI Conference, Wakefield, Mass., October 2000, pp. 26–27). However, not all logic functions can be effectively realized with just inverters and NOR gates, it is often desirable to also have NAND gates.
The mirrored configuration of FIG. 2A is referred to as the pseudo-pMOS circuit and is shown in FIG. 2B. (See generally, R. Rajsuman et al., “CMOS stuck-open fault detection using single test patterns,” 26th ACM/IEEE Design Automation Conference.” 25–29 Jun. 1989, Las Vegas, Nev., pp. 714–17, 1989; and U.S. Pat. 5,315,301 “Binary data generating circuit and A/D converter having immunity to noise,” 24 May 1994). The pseudo-pMOS illustrated in FIG. 2B is a 2-input positive logic NAND gate and provides a positive logic NAND circuit function. Pseudo-CMOS static logic is then a combination of pseudo-nMOS (FIG. 2A) and pseudo-pMOS gates (FIG. 2B). However, pseudo-CMOS static logic is slow due to the slow pull up of the pMOS devices in NAND gates which must charge the output high if any of the NAND gate inputs, e.g. C or D, is low.
Therefore, there is a need in the art to provide CMOS gate arrays which result in faster switching speeds, use less power, use far fewer devices to conserve chip surface space, and which require much less wiring and circuit complexity that conventional logic array approaches.